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USB2502
2-Port USB 2.0 Hub Controller
PRODUCT FEATURES
Integrated USB 2.0 Compatible 2-Port Hub
-- High-Speed (480Mbits/s), Full-Speed (12Mbits/s) and Low-Speed (1.5Mbits/s) compatible -- Full power management with ganged power control -- Detects Bus-Power/Self-Power source and changes mode automatically
Datasheet On-Board 24MHz Crystal Driver Circuit or 24 MHz external clock driver Internal PLL for 480MHz USB 2.0 Sampling Internal 1.8V Linear Voltage Regulator Integrated USB termination and Pull-up/Pull-down resistors Internal Short Circuit protection of USB differential signal pins Basic single-color LED support 1.8 Volt Low Power Core Operation 3.3 Volt I/O with 5V Input Tolerance 36 Pin QFN or 48 Pin TQFP lead-free RoHS compliant package
Complete USB Specification 2.0 Compatibility
-- Includes USB 2.0 Transceivers
VID/PID/DID, and Port Configuration for Hub via:
-- Single Serial I2C EEPROM -- SMBus Slave Port
Default VID/PID/DID, allows functionality when configuration EEPROM is absent Hardware Strapping options allow for configuration without an external EEPROM or SMBus Host
SMSC USB2502
DATASHEET
Revision 2.1 (12-06-06)
2-Port USB 2.0 Hub Controller Datasheet
ORDER NUMBERS: USB2502-AEZG FOR 36 PIN LEAD-FREE ROHS COMPLIANT QFN PACKAGE; USB2502-HT FOR 48 PIN LEAD-FREE ROHS COMPLIANT TQFP PACKAGE
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2006 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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2-Port USB 2.0 Hub Controller Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 OEM Selectable Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 2 Pin Table 2-Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pin Configuration 2-Port Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 4 2-Port Hub Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 5 Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 5.2 2-Port Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Hub Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 VBus Detect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 In-Circuit EEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 EEPROM DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Invalid Protocol Response Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.3 General Call Address Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 Slave Device Time-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 Stretching the SCLK Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.6 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.7 Bus Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.8 SMBus Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.9 Internal SMBus Memory Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Configuration Option: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Strapping Options: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 External Hardware RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 18 19 19 19 19 24 24 25 25 26 26 26 26 26 26 32 32 32 33 36
5.3
5.4 5.5 5.6
Chapter 6 XNOR Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 7 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.1 7.2 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Chapter 8 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1 Oscillator/Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.1 SMBus Interface: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.2 I2C EEPROM: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1.3 USB 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 42 42 42
Chapter 9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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List of Tables
Table 2.1 Table 2.2 Table 4.1 Table 4.2 Table 4.3 Table 4.4 Table 4.5 Table 5.1 Table 5.2 Table 5.3 Table 5.4 Table 5.5 Table 5.6 Table 5.7 Table 7.1 Table 9.1 2-Port Pin Table for 36-QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2-Port Pin Table for 48-TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-Port Hub Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus or EEPROM Interface Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power, Ground, and No Connect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 User-Defined Descriptor Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SMBus Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SMBus Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SMBus Slave Interface Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Reset_N Timing for Default/Strap Option Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 48 Pin TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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List of Figures
Figure 3.1 Figure 3.2 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 9.1 Figure 9.2 2-Port 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2-Port 48-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2-Port Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LED Strapping Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset_N Timing for Default/Strap Option Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset_N Timing for EEPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reset_N Timing for SMBus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 48 Pin TQFP Package Outline (7x7x1.4 mm body, 2mm Footprint) . . . . . . . . . . . . . . . . . . . 44
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Chapter 1 General Description
The SMSC 2-Port Hub is fully compliant with the USB 2.0 Specification and will attach to a USB host as a Full-Speed Hub or as a Full-/High-Speed Hub. The 2-Port Hub supports Low-Speed, Full-Speed, and High-Speed (if operating as a High-Speed Hub) downstream devices on all of the enabled downstream ports. The Hub works with an external USB power distribution switch device to control VBUS switching to downstream ports, and to limit current and sense over-current conditions. All required resistors on the USB ports are integrated into the Hub. This includes all series termination resistors on D+ and D- pins and all required pull-down and pull-up resistors on D+ and D- pins. The over-current sense inputs for the downstream facing ports have internal pull-up resistors. Throughout this document the upstream facing port of the hub will be referred to as the upstream port, and the downstream facing ports will be called the downstream ports.
1.1
OEM Selectable Features
A default configuration is available in the USB2502 following a reset. This configuration may be sufficient for some applications. Strapping option pins make it possible to modify a limited sub-set of the configuration options. The USB2502 may also be configured by an external EEPROM or a microcontroller. When using the microcontroller interface, the Hub appears as an SMBus slave device. If the Hub is pin-strapped for external EEPROM configuration but no external EEPROM is present, then a value of `0' will be written to all configuration data bit fields (the hub will attach to the host with all `0' values). The 2-Port Hub supports several OEM selectable features: Operation as a Self-Powered USB Hub or as a Bus-Powered USB Hub. Operation as a Dynamic-Powered Hub (Hub operates as a Bus-Powered device if a local power source is not available and switches to Self-Powered operation when a local power source is available). Optional OEM configuration via I2C EEPROM or via the industry standard SMBus interface from an external SMBus Host. Compound device support (port is permanently hardwired to a downstream USB peripheral device). Hardware strapping options enable configuration of the following features. Non-Removable Ports Port Power Polarity (active high or active low logic)
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Chapter 2 Pin Table 2-Port
Table 2.1 2-Port Pin Table for 36-QFN UPSTREAM USB 2.0 INTERFACE (3 PINS) USBDP0 USBDN0 VBUS_DET
2-PORT USB 2.0 INTERFACE (10 PINS) USBDP1 GR1/ NON_REM0 PRTPWR USBDN1 GR2/ NON_REM1 OCS_N SERIAL PORT INTERFACE (3 PINS) SDA/SMBDATA SCL/SMBCLK/ CFG_SEL0 MISC (7 PINS) XTAL1/CLKIN ATEST/ REG_EN XTAL2 CLKIN_EN RESET_N TEST SELF_PWR CFG_SEL1 USBDP2 PRTPWR_POL USBDN2 RBIAS
POWER, GROUND (13 PINS)
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Table 2.2 2-Port Pin Table for 48-TQFP UPSTREAM USB 2.0 INTERFACE (3 PINS) USBDP0 USBDN0 VBUS_DET
2-PORT USB 2.0 INTERFACE (10 PINS) USBDP1 GR1/ NON_REM0 PRTPWR USBDN1 GR2/ NON_REM1 OCS_N SERIAL PORT INTERFACE (3 PINS) SDA/SMBDATA SCL/SMBCLK CFG_SEL0 MISC (7 PINS) XTAL1/CLKIN ATEST/ REG_EN XTAL2 CLKIN_EN RESET_N TEST SELF_PWR CFG_SEL1 USBDP2 PRTPWR_POL USBDN2 RBIAS
POWER, GROUND AND NO CONNECT (25 PINS)
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Chapter 3 Pin Configuration 2-Port Hub
SCL/SMBCLK/CFG_SEL0 20
21
23
22
25
26
24
27
VDD33CR VSS XTAL2 XTAL1/CLKIN VDDA18PLL VDDA33PLL ATEST/REG_EN RBIAS VSS
28 29 30 31 32 33 34 35 36
1 4 3 5 7 2 6 8 9
19
SDA/SMBDATA
VBUS_DET
VDD18
RESET_N
VSS
CLKIN_EN
TEST
CFG_SEL1
18 17 16
VDD18 VSS SELF_PWR OCS_N PRTPWR PRTPWR_POL GR2/NON_REM1 GR1/NON_REM0 VSS
SMSC USB2502 (Top View QFN-36)
Thermal Slug (must be connected to VSS)
15 14 13 12 11 10
VDDA33
VSS
USBDN0
USBDN1
VDDA33
Indicates pins on the bottom of the device.
Figure 3.1 2-Port 36-Pin QFN
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USBDN2
USBDP0
USBDP1
USBDP2
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Figure 3.2 2-Port 48-Pin TQFP
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Chapter 4 2-Port Hub Block Diagram
VBUS
Upstream USB Data 3.3V
24 MHz Crystal
To EEPROM or SMBus Master 1.8V SD SCK
PLL Bus-Power Upstream PHY 1.8V Reg
Serial Interface
Repeater
SIE
Controller
Transaction Translator
Port Controller
Routing Logic
Downstream PHY #1
OC Sense Switch Driver LED Driver Strapping Options
Downstream PHY #2
Downstream USB Data
OC Sense
Switch/LED Driver/optis
Downstream USB Data
Figure 4.1 2-Port Block Diagram Table 4.1 2-Port Hub Pin Descriptions NAME SYMBOL TYPE UPSTREAM USB 2.0 INTERFACE FUNCTION
USB Bus Data Detect Upstream VBUS Power
USBDN0 USBDP0 VBUS_DET
IO-U I/O8
These pins connect to the upstream USB bus data signals. Detects state of Upstream VBUS power. The SMSC Hub monitors VBUS_DET to determine when to assert the internal D+ pull-up resistor (signalling a connect event). When designing a detachable hub, this pin must be connected to the VBUS power pin of the USB port that is upstream of the hub. (Use of a weak pull-down resistor is recommended.) For self-powered applications with a permanently attached host, this pin must be pulled-up to either 3.3V or 5.0V (typically VDD33).
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Table 4.1 2-Port Hub Pin Descriptions (continued) NAME SYMBOL TYPE 2-PORT USB 2.0 HUB INTERFACE FUNCTION
High-Speed USB Data USB Power Enable
USBDN[2:1] USBDP[2:1] PRTPWR
IO-U O8
These pins connect to the downstream USB peripheral devices attached to the Hub's ports. Enables power to USB peripheral devices (downstream). The active signal level of the PRTPWR pin is determined by the Power Polarity Strapping function of the PRTPWR_POL pin.
Port [2:1] Green LED & Port NonRemovable strapping option.
GR[2:1]/ NON_REM[1:0]
I/O8
Green indicator LED for ports 2 and 1. Will be active low when LED support is enabled via EEPROM or SMBus. If the hub is configured by the internal default configuration, these pins will be sampled at the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) to determine if ports [2:1] contain permanently attached (non-removable) devices. Also, the active state of the LED's will be determined as follows: NON_REM[1:0] = `00', All ports are removable, GR2 is active high, GR1 is active high. NON_REM1:0] = `01', Port 1 is non-removable, GR2 is active high, GR1 is active low. NON_REM[1:0] = `10', Ports 1 & 2 are non-removable, GR2 is active low, GR1 is active high. NON_REM[1:0] = `11', Ports 1 & 2 are non-removable, GR2 is active low, GR1 is active low.
Port Power Polarity strapping.
PRTPWR_POL
I/O8
Port Power Polarity strapping determination for the active signal polarity of the PRTPWR pin. While RESET_N is asserted, the logic state of this pin will (though the use of internal combinatorial logic) determine the active state of the PRTPWR pin in order to ensure that downstream port power is not inadvertently enabled to inactive ports during a hardware reset. On the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1), the logic value will be latched internally, and will retain the active signal polarity for the PRTPWR pin. `1' = PRTPWR pin has an active `high' polarity `0' = PRTPWR pin has an active `low' polarity
Over Current Sense USB Transceiver Bias
OCS_N
IPU
Input from external current monitor indicating an overcurrent condition. {Note: Contains internal pull-up to 3.3V supply} A 12.0k (+/- 1%) resistor is attached from ground to this pin to set the transceiver's internal bias settings.
RBIAS
I-R
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Table 4.1 2-Port Hub Pin Descriptions (continued) NAME SYMBOL TYPE SERIAL PORT INTERFACE FUNCTION
Serial Data/SMB Data Serial Clock/SMB Clock & Config Select 0 Configuration Programming Select
SDA/SMBDATA SCL/SMBCLK/ CFG_SEL0
IOSD12 IOSD12
(Serial Data)/(SMB Data) signal. (Serial Clock)/(SMB Clock) signal. This multifunction pin is read on the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) and will determine the hub configuration method as described in Table 4.2. This pin is read on the rising edge of RESET_N (see the applicable RESET_N timing table in Section 5.6.1) and will determine the hub configuration method as described in Table 4.2.
CFG_SEL1
I
Table 4.2 SMBus or EEPROM Interface Behavior
CFG_SEL1 0 0 1 1
CFG_SEL0 0 1 0 1
SMBus or EEPROM interface behavior. Reserved Configured as an SMBus slave for external download of userdefined descriptors. SMBus slave address is 0101100 Internal Default Configuration via strapping options. 2-wire (I2C) EEPROMS are supported,
Table 4.3 Miscellaneous Pins NAME SYMBOL TYPE FUNCTION
Crystal Input/External Clock Input Crystal Output
XTAL1/ CLKIN XTAL2
ICLKx
24MHz crystal or external clock input. This pin connects to either one terminal of the crystal or to an external 24MHz clock when a crystal is not used. 24MHz Crystal This is the other terminal of the crystal, or left unconnected when an external clock source is used to drive XTAL1/CLKIN. It must not be used to drive any external circuitry other than the crystal circuit. Clock In Enable: Low = XTAL1 and XTAL2 pins configured for use with external crystal High = XTAL1 pin configured as CLKIN, and must be driven by an external CMOS clock. This active low signal is used by the system to reset the chip. The minimum active low pulse is 1us. Detects availability of local self-power source. Low = Self/local power source is NOT available (i.e., Hub gets all power from Upstream USB VBus). High = Self/local power source is available. Used for testing the chip. User must treat as a noconnect or connect to ground.
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OCLKx
Clock Input Enable
CLKIN_EN
I
RESET Input Self-Power / Bus-Power Detect TEST Pin
RESET_N SELF_PWR
IS I
TEST
IPD
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Table 4.3 Miscellaneous Pins (continued) NAME SYMBOL TYPE FUNCTION
Analog Test & Internal 1.8V voltage regulator enable
ATEST/ REG_EN
AIO
This signal is used for testing the analog section of the chip, and to enable or disable the internal 1.8v regulator. This pin must be connected to VDDA33 to enable the internal 1.8V regulator, or to VSS to disable the internal regulator. When the internal regulator is enabled, the 1.8V power pins must be left unconnected, except for the required bypass capacitors.When the PHY is in test mode, the internal regulator is disabled and the ATEST pin functions as a test pin.
Table 4.4 Power, Ground, and No Connect NAME SYMBOL TYPE FUNCTION
VDDCORE3P3
VDD33CR
+3.3V I/O Power. If the internal core 1.8V regulator is enabled, then this pin acts as the regulator input
VDD1P8
VDD18
+1.8V core power. If the internal regulator is enabled, then VDD18 pin 27 must have a 4.7F (or greater) 20% (ESR <0.1) capacitor to VSS
VDDAPLL3P3
VDDA33PLL
+3.3V Filtered analog power for the internal PLL If the internal PLL 1.8V regulator is enabled, then this pin acts as the regulator input
VDDAPLL1P8
VDDA18PLL
+1.8V Filtered analog power for internal PLL. If the internal regulator is enabled, then this pin must have a 4.7F (or greater) 20% (ESR <0.1) capacitor to VSS
VDDA3P3 VSS
VDDA33 VSS
+3.3V Filtered analog power. Ground.
Table 4.5 Buffer Type Descriptions BUFFER DESCRIPTION
I IPD IPU IS I/O8 O8
Input. Input, with a weak Internal pull-down. Input, with a weak Internal pull-up. Input with Schmitt trigger. Input/Output 8mA Output 8mA
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Table 4.5 Buffer Type Descriptions (continued) BUFFER DESCRIPTION
IOSD12 ICLKx OCLKx I-R IO-U
Open drain....12mA sink with Schmitt trigger, and must meet I2C-Bus Specification Version 2.1 requirements. XTAL Clock Input XTAL Clock Output RBIAS Defined in USB Specification. Note: Meets USB 1.1 requirements when operating as a 1.1-compliant device and meets USB 2.0 requirements when operating as a 2.0-compliant device. Analog Input/output. Per PHY test requirements.
AIO
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Chapter 5 Functional Block Description
5.1 2-Port Hub
SMSC's USB 2.0 2-Port Hub is fully specification compliant to the Universal Serial Bus Specification Revision 2.0 April 27,2000 (12/7/2000 and 5/28/2002 Errata). Please reference Chapter 11 (Hub Specification) for general details regarding Hub operation and functionality. For performance reasons, the 2-Port Hub provides 1 Transaction Translator (TT) per port (defined as Multi-TT configuration), divided into 4 non-periodic buffers per TT.
5.1.1
Hub Configuration Options
The SMSC Hub supports a large number of features and must be configured in order to correctly function when attached to a USB host controller. There are three principal ways to configure the hub: SMBus, EEPROM, or by internal default settings. In all cases, the configuration method will be determined by the CFG_SEL1 and CFG_SEL0 pins immediately after RESET_N negation.
5.1.1.1
Vendor ID
Is a 16-bit value that uniquely identifies the Vendor of the user device (assigned by USB-Interface Forum). This field is set by the OEM using either the SMBus or EEPROM interface options. When using the internal default option, SMSC's VID (see Table 5.1) will be reported.
5.1.1.2
Product ID
Is a 16-bit value that the Vendor can assign that uniquely identifies this particular product (assigned by OEM). This field is set by the OEM using either the SMBus or EEPROM interface options. When using the internal default option, SMSC's PID designation of (see Table 5.1) will be reported.
5.1.1.3
Device ID
Is a 16-bit device release number in BCD format (assigned by OEM). This field is set by the OEM using either the SMBus or EEPROM interface options. When using the internal default option, SMSC's DID designation of (see Table 5.1) will be reported.
5.1.1.4
Self-Powered/Bus-Powered
The Hub is either Self-Powered (draws less than 2mA of upstream bus power) or Bus-Powered (limited to a 100mA maximum of upstream power prior to being configured by the host controller). When configured as a Bus-Powered device, the SMSC Hub consumes less than 100mA of current prior to being configured. After configuration, the Bus-Powered SMSC Hub (along with all associated hub circuitry, any embedded devices if part of a compound device, and 100mA per externally available downstream port) must consume no more than 500mA of upstream VBUS current. The current consumption is system dependent, and the OEM must ensure that the USB 2.0 specifications are not violated. When configured as a Self-Powered device, <1mA of upstream VBUS current is consumed and all 7 ports are available, with each port being capable of sourcing 500mA of current. This field is set by the OEM using either the SMBus or EEPROM interface options. When using the internal default option, the SELF_PWR pin determines the Self-powered or Bus-powered status. Please see the description under Dynamic Power for the self/bus power functionality when dynamic power switching is enabled.
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5.1.1.5
High-Speed Disable
Allows an OEM to force the Hub to configure as a Full-Speed device only (i.e. High-Speed not available). This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.6
EOP Disable
During FS operation only, this permits the Hub to send EOP if no downstream traffic is detected at EOF1. See Section 11.3.1 of the USB 2.0 Specification for additional details. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.7
Current Sensing
Selects current sensing as all ports ganged, or none. This field can be set by the OEM using either the SMBus or EEPROM interface options.When using the internal default option, the SELF_PWR pin determines if current sensing will be ganged, or none (ganged if self-powered, none if bus-powered)
5.1.1.8
Compound Device
Allows the OEM to indicate that the Hub is part of a compound (see the USB Specification for definition) device. The applicable port(s) must also be defined as having a "Non-Removable Device". This field is set by the OEM using either the SMBus or EEPROM interface options. Note: When configured via strapping options, declaring a port as non-removable automatically causes the hub controller to report that it is part of a compound device.
5.1.1.9
Non-Removable Device
Informs the Host if one of the active ports has a permanent device that is undetachable from the Hub. (Note: The device must provide its own descriptor data.) This field is set by the OEM using either the SMBus or EEPROM interface options. When using the internal default option, the NON_REM[1:0] pins will designate the appropriate ports as being nonremovable.
5.1.1.10
Self-Powered Port DISABLE
During Self-Powered operation, this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a Host Controller. The disabled ports must be in decreasing order starting with port 2. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.11
Bus-Powered Port DISABLE
During Bus-Powered operation, this selects the ports which will be permanently disabled, and are not available to be enabled or enumerated by a Host Controller. The disabled ports must be in decreasing order starting with port 2. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.12
Dynamic Power
Controls the ability of the 2-Port Hub to automatically change from Self-Powered operation to BusPowered operation if the local power source is removed or is unavailable (and from Bus-Powered to Self-Powered if the local power source is restored). {Note: If the local power source is available, the 2-port Hub will always switch to Self-Powered operation.}
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When Dynamic Power switching is enabled, the Hub detects the availability of a local power source by monitoring the external SELF_PWR pin. If the Hub detects a change in power source availability, the Hub immediately disconnects and removes power from all downstream devices and disconnects the upstream port. The Hub will then re-attach to the upstream port as either a Bus-Powered Hub (if local-power in unavailable) or a Self-Powered Hub (if local power is available). This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.13
Over-Current Timer
The time delay (in 2ms increments) for an over-current condition to persist before it is reported to the Host. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.14
Self-Powered Max Power
When in Self-Powered configuration, Sets value in 2mA increments. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.15
Bus-Powered Max Power
When in Bus-Powered configuration, Sets value in 2mA increments. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.16
Self-powered Hub Controller Current
When in Self-Powered configuration, Maximum current requirements of the Hub Controller in 2mA increments. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.17
Bus-Powered Hub Controller Current
When in Bus-Powered configuration, Maximum current requirements of the Hub Controller in 2mA increments. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.18
Power-On Timer
Time (in 2ms intervals) from the time power-on sequence begins on a port until power is good on that port. System software uses this value to determine how long to wait before accessing a powered-on port. This field is set by the OEM using either the SMBus or EEPROM interface options.
5.1.1.19
Power Switching Polarity
The selection of active state "polarity" for the PRTPWR2 pin is made by a strapping option only.
5.1.2
VBus Detect
According to Section 7.2.1 of the USB 2.0 Specification, a downstream port can never provide power to its D+ or D- pull-up resistors unless the upstream port's VBUS is in the asserted (powered) state. The VBUS_DET pin on the Hub monitors the state of the upstream VBUS signal and will not pull-up the D+ or D- resistor if VBUS is not active. If VBUS goes from an active to an inactive state (Not Powered), Hub will remove power from the D+ or D- pull-up resistor within 10 seconds.
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5.2
EEPROM Interface
The SMSC Hub can be configured via a 2-wire (I2C) EEPROM. (Please see Table 4.1, "2-Port Hub Pin Descriptions" for specific details on how to enable the I2C EEPROM option). The Internal state-machine will, (when configured for EEPROM support) read the external EEPROM for configuration data. The hub will then "attach" to the upstream USB host. Please see Table 5.1 User-Defined Descriptor Data for a list of data fields available.
5.2.1
I2C EEPROM
The I2C EEPROM interface implements a subset of the I2C Master Specification (Please refer to the Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The Hub's I2C EEPROM interface is designed to attach to a single "dedicated" I2C EEPROM, and it conforms to the Standard-mode I2C Specification (100kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility.
Note: Extensions to the I2C Specification are not supported.
The Hub acts as the master and generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which device acts as the receiver), and generates the START and STOP conditions.
5.2.1.1
Implementation Characteristics
Please refer to the MicroChip 24AA00 DataSheet for Protocol and Programming specifics.
5.2.1.2
Pull-Up Resistor
The Circuit board designer is required to place external pull-up resistors (10K recommended) on the SDA/SMBDATA & SCL/SMBCLK/CFG_SELO lines (per SMBus 1.0 Specification, and EEPROM manufacturer guidelines) to Vcc in order to assure proper operation.
5.2.1.3
I2C EEPROM Slave Address
Slave address is 1010000.
Note: 10-bit addressing is NOT supported.
5.2.2
In-Circuit EEPROM Programming
The EEPROM can be programmed via ATE by pulling RESET_N low (which tri-states the Hub's EEPROM interface and allows an external source to program the EEPROM).
5.2.3
EEPROM DATA
Table 5.1 User-Defined Descriptor Data DEFAULT CFG SELF (HEX) DEFAULT CFG BUS (HEX)
FIELD
BYTE MSB: LSB
SIZE (BYTES)
DESCRIPTION
VID PID DID
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1:0 3:2 5:4
2 2 2
0424 2502 0000
0424 2502 0000
19
Vendor ID (assigned by USB-IF). Product ID (assigned by Manufacturer). Device ID (assigned by Manufacturer).
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Table 5.1 User-Defined Descriptor Data (continued) DEFAULT CFG SELF (HEX) DEFAULT CFG BUS (HEX)
FIELD
BYTE MSB: LSB
SIZE (BYTES)
DESCRIPTION
Config Data Byte 1 Config Data Byte 2 Non Removable Device Port Disable Self-Powered Port Disable Bus-Powered Max Power Self-Powered Max Power Bus-Powered Hub Controller Max Current Self-Powered Hub Controller Max Current Bus-Powered Power-On Time
6 7 8
1 1 1
88 90 00
0C 90 00
Configuration data byte #1 for Hub options. Configuration data byte #2 for Hub options. Defines the ports that contain attached devices (this is used only when Hub is part of a compound device). Selects the ports that will be permanently disabled Selects the ports that will be permanently disabled Max Current for this configuration (expressed in 2mA units). Max Current for this configuration (expressed in 2mA units). Max Current (expressed in 2mA units).
9 A B C D
1 1 1 1 1
00 00 01 64 01
00 00 01 64 01
E
1
64
64
Max Current (expressed in 2mA units).
F
1
32
32
Time until power is stable.
5.2.3.1
BIT NUMBER
EEPROM Offset 1:0(h) - Vendor ID
BIT NAME
DESCRIPTION
15:8 7:0
VID_MSB VID_LSB
Most Significant Byte of the Vendor ID. Least Significant Byte of the Vendor ID.
5.2.3.2
BIT NUMBER
EEPROM Offset 3:2(h) - Product ID
BIT NAME
DESCRIPTION
15:8 7:0
PID_MSB PID_LSB
Most Significant Byte of the Product ID. Least Significant Byte of the Product ID.
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5.2.3.3
BIT NUMBER
EEPROM Offset 5:4(h) - Device ID
BIT NAME
DESCRIPTION
15:8 7:0
DID_MSB DID_LSB
Most Significant Byte of the Device ID. Least Significant Byte of the Device ID.
5.2.3.4
BIT NUMBER
EEPROM Offset 6(h) - CONFIG_BYTE_1
BIT NAME
DESCRIPTION
7
SELF_BUS_PWR
Self or Bus Power: Selects between Self- and Bus-Powered operation. 0 = Bus-Powered operation. (BUS Default) 1 = Self-Powered operation. (SELF Default) Note: If Dynamic Power Switching is enabled, this bit is ignored and the SELF_PWR pin is used to determine if the hub is operating from self or bus power.
6 5
Reserved HS_DISABLE
Reserved High Speed Disable: Disables the capability to attach as either a High/Fullspeed device, and forces attachment as Full-speed only i.e. (no High-Speed support). 0 = High-/Full-Speed. (Default) 1 = Full-Speed-Only (High-Speed disabled!)
4 3
Reserved EOP_DISABLE
Reserved EOP Disable: Disables EOP generation at EOF1 when no downstream directed traffic is in progress. 0 = EOP generation at EOF1 is enabled. 1 = EOP generation at EOF1 is disabled, (normal operation). (Default)
2:1
CURRENT_SNS
Over Current Sense: Indicates whether current sensing is ganged. 00 = Ganged sensing (all ports together). (Default for self-power) 01 = Reserved 1x = Over current sensing not supported. (may be used with Bus-Powered configurations only!, and is the default for bus-power)
0
Reserved
Reserved
5.2.3.5
BIT NUMBER
EEPROM Offset 7(h) - CONFIG_BYTE_2
BIT NAME
DESCRIPTION
7
DYNAMIC
Dynamic Power Enable: Controls the ability for the Hub to transition to BusPowered operation if the local power source is removed (can revert back to Self-Power if local power source is restored). 0 = No Dynamic auto-switching. 1 = Dynamic Auto-switching capable.(Default)
6
Reserved
Reserved
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BIT NUMBER
BIT NAME
DESCRIPTION
5:4
OC_TIMER
OverCurrent Timer: Over Current Timer delay. 00 = 0.1ms 01 = 2ms (Default) 10 = 4ms 11 = 6ms
3
COMPOUND
Compound Device: Designates if Hub is part of a compound device. 0 = No. (Default) 1 = Yes, Hub is part of a compound device.
2:0
Reserved
Reserved.
5.2.3.6
BIT NUMBER
EEPROM Offset 8(h) - Non-Removable Device
BIT NAME
DESCRIPTION
7:0
NR_DEVICE
Non-Removable Device: Indicates which port(s) include non-removable devices. `0' = port is removable, `1' = port is non-removable. Bit 7:3= 0; Reserved Bit 2= 1; Port 2 non-removable. Bit 1= 1; Port 1 non removable. Bit 0 is Reserved, always = `0'.
5.2.3.7
BIT NUMBER
EEPROM Offset 9(h) - Port Disable For Self Powered Operation
BIT NAME
DESCRIPTION
7:0
PORT_DIS_SP
Port Disable Self-Powered: Disables 1 or more contiguous ports. `0' = port is available, `1' = port is disabled. Bit 7:3= 0; Reserved Bit 2= 1; Port 2 is disabled. Bit 1= 1; Port 1 is disabled. Bit 0 is Reserved, always = `0'
5.2.3.8
BIT NUMBER
EEPROM Offset A(h) - Port Disable For Bus Powered Operation
BIT NAME
DESCRIPTION
7:0
PORT_DIS_BP
Port Disable Bus-Powered: Disables 1 or more contiguous ports. `0' = port is available, `1' = port is disabled. Bit 7:3= 0; Reserved Bit 2= 1; Port 2 is disabled. Bit 1= 1; Port 1 is disabled. Bit 0 is Reserved, always = `0'
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5.2.3.9
BIT NUMBER
EEPROM Offset B(h) - Max Power For Self Powered Operation
BIT NAME
DESCRIPTION
7:0
MAX_PWR_SP
Max Power Self_Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. Note: The USB 2.0 Specification does not permit this value to exceed 100mA A value of 50 (decimal) indicates 100mA.
5.2.3.10
BIT NUMBER
EEPROM Offset C(h) - Max Power For Bus Powered Operation
BIT NAME
DESCRIPTION
7:0
MAX_PWR_BP
Max Power Bus_Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a bus-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. A value of 50 (decimal) indicates 100mA.
5.2.3.11
BIT NUMBER
EEPROM Offset D(h) - Hub Controller Max Current For Self Powered Operation
BIT NAME
DESCRIPTION
7:0
HC_MAX_C_SP
Hub Controller Max Current Self-Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a selfpowered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. Note: The USB 2.0 Specification does not permit this value to exceed 100mA A value of 50 (decimal) indicates 100mA, which is the default value.
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5.2.3.12
BIT NUMBER
EEPROM Offset E(h) - Hub Controller Max Current For Bus Powered Operation
BIT NAME
DESCRIPTION
7:0
HC_MAX_C_BP
Hub Controller Max Current Bus-Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a selfpowered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. A value of 50 (decimal) indicates 100mA, which is the default value.
5.2.3.13
BIT NUMBER
EEPROM Offset F(h) - Power-On Time
BIT NAME
DESCRIPTION
7:0
POWER_ON_TIME
Power On Time: The length of time that is takes (in 2 ms intervals) from the time the host initiated power-on sequence begins on a port until power is good on that port.
5.3
SMBus Slave Interface
Instead of loading User-Defined Descriptor data from an external EEPROM, the SMSC Hub can be configured to receive a code load from an external processor via an SMBus interface. The SMBus interface shares the same pins as the EEPROM interface, if CFG_SEL1 & CFG_SEL0 activates the SMBus interface, external EEPROM support is no longer available (and the user-defined descriptor data must be downloaded via the SMBus). Due to system issues, the SMSC Hub waits indefinitely for the SMBus code load to complete and only "appears" as a newly connected device on USB after the code load is complete. The Hub's SMBus implementation is a subset of the SMBus interface to the host. The device is a slave-only SMBus device. The implementation in the device is a subset of SMBus since it only supports two protocols. The Write Byte and Read Byte protocols are the only valid SMBus protocols for the Hub. The Hub responds to other protocols as described in Section 5.3.2, "Invalid Protocol Response Behavior," on page 25. Reference the System Management Bus Specification, Rev 1.0. The SMBus interface is used to read and write the registers in the device. The register set is shown in Section 5.3.9, "Internal SMBus Memory Register Set," on page 26.
5.3.1
Bus Protocols
Typical Write Byte and Read Byte protocols are shown below. Register accesses are performed using 7-bit slave addressing, an 8-bit register address field, and an 8-bit data field. The shading indicates the Hub driving data on the SMBDATA line; otherwise, host data is on the SDA/SMBDATA line. The slave address is the unique SMBus Interface Address for the Hub that identifies it on SMBus. The register address field is the internal address of the register to be accessed. The register data field is the data that the host is attempting to write to the register or the contents of the register that the host is attempting to read.
Note: Data bytes are transferred MSB first (msb first).
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5.3.1.1
Byte Protocols
When using the Hub SMBus Interface for byte transfers, a write will always consist of the SMBus Interface Slave Address byte, followed by the Internal Address Register byte, then the data byte. The normal read protocol consists of a write to the HUB with the SMBus Interface Address byte, followed by the Internal Address Register byte. Then restart the Serial Communication with a Read consisting of the SMBus Interface Address byte, followed by the data byte read from the Hub. This can be accomplished by using the Read Byte protocol.
Note: For the following SMBus tables:
Denotes Master-to-Slave
Write Byte
Denotes Slave-to-Master
The Write Byte protocol is used to write data to the registers. The data will only be written if the protocol shown in Table 5.2 is performed correctly. Only one byte is transferred at a time for a Write Byte protocol.
Table 5.2 SMBus Write Byte Protocol
Field: Bits:
Start 1
Slave Addr 7
Wr 1
Ack 1
Reg. Addr 8
Ack 1
Reg. Data 8
Ack 1
Stop 1
Read Byte The Read Byte protocol is used to read data from the registers. The data will only be read if the protocol shown in Table 5.3 is performed correctly. Only one byte is transferred at a time for a Read Byte protocol.
Table 5.3 SMBus Read Byte Protocol
Field: Bits:
Start 1
Slave Addr 7
Wr 1
Ack 1
Reg. Addr 8
Ack 1
Start 1
Slave Addr 7
Rd 1
Ack 1
Reg. Data 8
Nack 1
Stop 1
5.3.2
Invalid Protocol Response Behavior
Registers that are accessed with an invalid protocol are not updated. A register is only updated following a valid protocol. The only valid protocols are Write Byte and Read Byte, which are described above. The Hub only responds to the hardware selected Slave Address. Attempting to communicate with the Hub over SMBus with an invalid slave address or invalid protocol results in no response, and the SMBus Slave Interface returns to the idle state. The only valid registers that are accessible by the SMBus slave address are the registers defined in the Registers Section. See Section 5.3.3 for the response to undefined registers.
5.3.3
General Call Address Response
The Hub does not respond to a general call address of 0000_000b.
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5.3.4
Slave Device Time-Out
According to the SMBus Specification, V1.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (TTIMEOUT, MIN). Devices that have detected this condition must reset their communication and be able to receive a new START condition no later than 35ms (TTIMEOUT, MAX).
Note: Some simple devices do not contain a clock low drive circuit; this simple kind of device typically resets its communications port after a start or stop condition.
5.3.5
Stretching the SCLK Signal
The Hub supports stretching of the SCLK by other devices on the SMBus. The Hub does not stretch the SCLK.
5.3.6
SMBus Timing
The SMBus Slave Interface complies with the SMBus AC Timing Specification. See the SMBus timing in the "Timing Diagram" section.
5.3.7
Bus Reset Sequence
The SMBus Slave Interface resets and returns to the idle state upon a START field followed immediately by a STOP field.
5.3.8
SMBus Alert Response Address
The SMBALERT# signal is not supported by the Hub.
5.3.9
Internal SMBus Memory Register Set
The following table provides the SMBus slave interface register map values.
Table 5.4 SMBus Slave Interface Register Map
REG ADDR
R/W
REGISTER NAME
ABBR
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Status/Command VID LSB VID MSB PID LSB PID MSB DID LSB DID MSB Config Data Byte 1 Config Data Byte 2 Non-Removable Devices Port Disable (Self) Port Disable (Bus)
STCD VIDL VIDM PIDL PIDM DIDL DIDM CFG1 CFG2 NRD PDS PDB
7 7 7 7 7 7 7 7 7 7 7 7
26
6 6 6 6 6 6 6 6 6 6 6 6
5 5 5 5 5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4 4 4 4 4
3 3 3 3 3 3 3 3 3 3 3 3
2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0
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Table 5.4 SMBus Slave Interface Register Map (continued)
REG ADDR R/W REGISTER NAME ABBR BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB)
0Ch 0Dh 0Eh 0Fh 10h
R/W R/W R/W R/W R/W
Max Power (Self) Max Power (Bus) Hub Controller Max Current (Self) Hub Controller Max Current (bus) Power-on Time
MAXPS MAXPB HCMCS HCMCB PWRT
7 7 7 7 7
6 6 6 6 6
5 5 5 5 5
4 4 4 4 4
3 3 3 3 3
2 2 2 2 2
1 1 1 1 1
0 0 0 0 0
5.3.9.1
BIT NUMBER
Register 00h: Status/Command (Reset = 0x00)
BIT NAME
DESCRIPTION
7:3 2
Reserved RESET
Reserved. {Note: Software must never write a `1' to these bits} Reset the SMBus Interface and internal memory back to RESET_N assertion default settings. {Note: During this reset, this bit is automatically cleared to its default value of 0.} 0 = Normal Run/Idle State. 1 = Force a reset.
1
WRITE_PROT
Write Protect: The external SMBus host sets this bit after the Hub's internal memory is loaded with configuration data. {Note: The External SMBus Host is responsible for verification of downloaded data.} 0 = The internal memory (address range 01-10h) is not write protected. 1 = The internal memory (address range 01-10h) is "write-protected" to prevent unintentional data corruption.} {Note: This bit is write once and is only cleared by assertion of the external RESET_N pin.}
0
USB_ATTACH
USB Attach & power-down the SMBus Interface. 0 = Default; SMBus slave interface is active. 1 = Hub will signal a USB attach event to an upstream device, Note: SMBus Slave interface will completely power down after the ACK has completed. {Note: This bit is write once and is only cleared by assertion of the external RESET_N pin.}
5.3.9.2
BIT NUMBER
Register 01h: Vendor ID (LSB) (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
VID_LSB
Least Significant Byte of the Vendor ID.
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5.3.9.3
BIT NUMBER
Register 02h: Vendor ID (MSB) (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
VID_MSB
Most Significant Byte of the Vendor ID.
5.3.9.4
BIT NUMBER
Register 03h: Product ID (LSB) (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
PID_LSB
Least Significant Byte of the Product ID.
5.3.9.5
BIT NUMBER
Register 04h: Product ID (MSB) (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
PID_MSB
Most Significant Byte of the Product ID.
5.3.9.6
BIT NUMBER
Register 05h: Device ID (LSB) (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
DID_LSB
Least Significant Byte of the Device ID.
5.3.9.7
BIT NUMBER
Register 06h: Device ID (MSB) (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
DID_MSB
Most Significant Byte of the Device ID.
5.3.9.8
BIT NUMBER
Register 07h: CONFIG_BYTE_1 (Reset = 0x00)
BIT NAME
DESCRIPTION
7
SELF_BUS_PWR
Self or Bus Power: Selects between Self- and Bus-Powered operation. 0 = Bus-Powered operation. 1 = Self-Powered operation. Note: If Dynamic Power Switching is enabled, this bit is ignored and the SELF_PWR pin is used to determine if the hub is operating from self or bus power.
6
Reserved
Reserved
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BIT NUMBER
BIT NAME
DESCRIPTION
5
HS_DISABLE
High Speed Disable: Disables the capability to attach as either a High/Fullspeed device, and forces attachment as Full-speed only i.e. (no High-Speed support). 0 = High-/Full-Speed. 1 = Full-Speed-Only (High-Speed disabled!)
4 3
Reserved EOP_DISABLE
Reserved EOP Disable: Disables EOP generation of EOF1 when in Full-Speed mode. 0 = EOP generation is normal. 1 = EOP generation is disabled.
2:1
CURRENT_SNS
Over Current Sense: Indicates whether current sensing isganged. 00 = Ganged sensing (all ports together). 01 = Reserved1x = Over current sensing not supported. (must only be used with Bus-Powered configurations!)
0
Reserved
Reserved
5.3.9.9
BIT NUMBER
Register 08h: Configuration Data Byte 2 (Reset = 0x00)
BIT NAME
DESCRIPTION
7
DYNAMIC
Dynamic Power Enable: Controls the ability for the Hub to transition to BusPowered operation if the local power source is removed (can revert back to Self-Power if local power source is restored). 0 = No Dynamic auto-switching. 1 = Dynamic Auto-switching capable.
6 5:4
Reserved OC_TIMER
Reserved OverCurrent Timer: Over Current Timer delay. 00 = 0.1ms 01 = 2ms 10 = 4ms 11 = 6ms
3
COMPOUND
Compound Device: Designates if Hub is part of a compound device. 0 = No. 1 = Yes, Hub is part of a compound device.
2:0
Reserved
Reserved
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5.3.9.10
BIT NUMBER
Register 09h: Non-Removable Device (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
NR_DEVICE
Non-Removable Device: Indicates which port(s) include non-removable devices. `0' = port is removable, `1' = port is non-removable. Bit 7:3: Reserved, always = `0' Bit 2= 1; Port 2 non-removable. Bit 1= 1; Port 1 non removable. Bit 0 is Reserved, always = `0'.
5.3.9.11
BIT NUMBER
Register 0Ah: Port Disable For Self Powered Operation (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
PORT_DIS_SP
Port Disable Self-Powered: Disables 1 or more contiguous ports. `0' = port is available, `1' = port is disabled. Bit 7:3= 0; ReservedBit 2= 1; Port 2 is disabled. Bit 1= 1; Port 1 is disabled. Bit 0 is Reserved, always = `0'
5.3.9.12
BIT NUMBER
Register 0Bh: Port Disable For Bus Powered Operation (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
PORT_DIS_BP
Port Disable Bus-Powered: Disables 1 or more contiguous ports. `0' = port is available, `1' = port is disabled. Bit 7:3= 0; ReservedBit 2= 1; Port 2 is disabled. Bit 1= 1; Port 1 is disabled. Bit 0 is Reserved, always = `0'
5.3.9.13
BIT NUMBER
Register 0Ch: Max Power For Self Powered Operation (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
MAX_PWR_SP
Max Power Self_Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. Note: The USB 2.0 Specification does not permit this value to exceed 100mA A value of 50 (decimal) indicates 100mA.
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5.3.9.14
BIT NUMBER
Register 0Dh: Max Power For Bus Powered Operation (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
MAX_PWR_BP
Max Power Self_Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a self-powered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value also includes the power consumption of a permanently attached peripheral if the hub is configured as a compound device, and the embedded peripheral reports 0mA in its descriptors. A value of 50 (decimal) indicates 100mA.
5.3.9.15
BIT NUMBER
Register 0Eh: Hub Controller Max Current For Self Powered Operation (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
HC_MAX_C_SP
Hub Controller Max Current Self-Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a selfpowered hub. This value includes the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value does NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. Note: The USB 2.0 Specification does not permit this value to exceed 100mA A value of 50 (decimal) indicates 100mA, which is the default value.
5.3.9.16
BIT NUMBER
Register 0Fh: Hub Controller Max Current For Bus Powered Operation (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
HC_MAX_C_BP
Hub Controller Max Current Self-Powered: Value in 2mA increments that the Hub consumes from an upstream port (VBUS) when operating as a selfpowered hub. This value will include the hub silicon along with the combined power consumption (from VBUS) of all associated circuitry on the board. This value will NOT include the power consumption of a permanently attached peripheral if the hub is configured as a compound device. A value of 50 (decimal) would indicate 100mA, which is the default value.
5.3.9.17
BIT NUMBER
Register 10h: Power-On Time (Reset = 0x00)
BIT NAME
DESCRIPTION
7:0
POWER_ON_TIME
Power On Time: The length of time that is takes (in 2 ms intervals) from the time the host initiated power-on sequence begins on a port until power is good on that port.
5.3.9.18
Undefined Registers
The registers shown in Table 5.4 are the defined registers in the Hub. Reads to undefined registers return 00h. Writes to undefined registers have no effect and do not return an error.
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5.3.9.19
Reserved Registers
Unless otherwise instructed, only a `0' may be written to all reserved registers or bits.
5.4
Default Configuration Option:
The SMSC Hub can be configured via its internal default configuration. (please see for specific details on how to enable default configuration. Please refer to Table 5.1 on page 19 for the internal default values that are loaded when this option is selected.
5.5
Default Strapping Options:
The SMSC Hub can be configured via a combination of internal default values and pin strap options. Please see Table 4.1, "2-Port Hub Pin Descriptions" for specific details on how to enable the default/pin-strap configuration option. The strapping option pins only cover a limited sub-set of the configuration options. The internal default values will be used for the bits & registers that are not controlled by a strapping option pin. Please refer to Table 5.1 on page 19 for the internal default values that are loaded when this option is selected. The Green LED pins are sampled after RESET_N negation, and the logic values are used to configure the hub if the internal default configuration mode is selected. The implementation shown below (see Figure 5.1) shows a recommended passive scheme. When a pin is configured with a "Strap High" configuration, the LED functions with active low signalling, and the PAD will "sink" the current from the external supply. When a pin is configured with a "Strap Low" configuration, the LED functions with active high signalling, and the PAD will "source" the current to the external LED.
+V Strap High
50K
GR1
HUB GR2
50K
Strap Low
Figure 5.1 LED Strapping Option
5.6
Reset
There are two different resets that the Hub experiences. One is a hardware reset (via the RESET_N pin) and the second is a USB Bus Reset.
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5.6.1
External Hardware RESET_N
A valid hardware reset is defined as, assertion of RESET_N for a minimum of 1us after all power supplies are within operating range. While reset is asserted, the Hub (and its associated external circuitry) consumes less than 500A of current from the upstream USB power source (300A for the Hub and 200A for the external circuitry). Assertion of RESET_N (external pin) causes the following: 1. All downstream ports are disabled, and PRTPWR power to downstream devices is removed. 2. The PHYs are disabled, and the differential pairs will be in a high-impedance state. 3. All transactions immediately terminate; no states are saved. 4. All internal registers return to the default state (in most cases, 00(h)). 5. The external crystal oscillator is halted. 6. The PLL is halted. 7. LED indicators are disabled. The Hub is "operational" 500s after RESET_N is negated. Once operational, the Hub immediately reads OEM-specific data from the external EEPROM (if the SMBus option is not disabled).
5.6.1.1
RESET_N for Strapping Option Configuration
Drive Strap Outputs to inactive levels Start completion request response
Hardware reset asserted
Read Strap Options
Attach USB Upstream
USB Reset recovery
Idle
t1 t2
RESET_N
t5 t3
t6
t7
t8
VSS
t4
Strap Pins Don't Care VSS Valid Don't Care Driven by Hub if strap is an output.
Figure 5.2 Reset_N Timing for Default/Strap Option Mode Table 5.5 Reset_N Timing for Default/Strap Option Mode NAME DESCRIPTION MIN TYP MAX UNITS sec
t1 t2 t3 t4 t5
RESET_N Asserted. Strap Setup Time Strap Hold Time. hub outputs driven to inactive logic states USB Attach (See Note).
33
1 16.7 16.7 2.0 1400 1.5 100
nsec nsec
sec
msec
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Table 5.5 Reset_N Timing for Default/Strap Option Mode (continued) NAME DESCRIPTION MIN TYP MAX UNITS
t6 t7 t8
Host acknowledges attach and signals USB Reset. USB Idle. Completion time for requests (with or without data stage).
Notes:
100 undefined 5
msec msec msec
When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than 100mA from the upstream USB power source during t1+t5. All Power Supplies must have reached the operating levels mandated in Section Chapter 7, "DC Parameters", prior to (or coincident with) the assertion of RESET_N.
5.6.1.2
RESET_N for EEPROM Configuration
Start completion request response
Hardware reset asserted
Read Strap Options
Read EEPROM + Set Options
Attach USB Upstream
USB Reset recovery
Idle
t4 t1
RESET_N
t2
t3
t5
t6
t7
VSS
Figure 5.3 Reset_N Timing for EEPROM Mode Table 5.6 Reset_N Timing for EEPROM Mode NAME DESCRIPTION MIN TYP MAX UNITS sec
t1 t2 t3 t4 t5 t6 t7
RESET_N Asserted. Hub Recovery/Stabilization. EEPROM Read / Hub Config. USB Attach (See Note). Host acknowledges attach and signals USB Reset. USB Idle. Completion time for requests (with or without data stage).
Notes:
1 500 2.0 99.5 100 100 undefined 5
sec
msec msec msec msec msec
When in Bus-Powered mode, the Hub and its associated circuitry must not consume more than 100mA from the upstream USB power source during t4+t5+t6+t7.
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All Power Supplies must have reached the operating levels mandated in Section Chapter 7, "DC Parameters", prior to (or coincident with) the assertion of RESET_N.
5.6.1.3
RESET_N for SMBus Slave Configuration
Hardware reset asserted Reset Negation SMBus Code Load Hub PHY Stabilization Attach USB Upstream USB Reset recovery Idle Start completion request response
t1
RESET_N
t2
t3
t4
t5
t6
t7
VSS
Figure 5.4 Reset_N Timing for SMBus Mode Table 5.7 Reset_N Timing for SMBus Mode NAME DESCRIPTION MIN TYP MAX UNITS sec
t1 t2 t3 t4 t5 t6 t7
RESET_N Asserted. Hub Recovery/Stabilization. SMBus Code Load (See Note). Hub Configuration and USB Attach. Host acknowledges attach and signals USB Reset. USB Idle. Completion time for requests (with or without data stage).
Notes:
1 500 10 99.5 100 100 Undefined 5
sec
msec msec msec msec msec
For Bus-Powered configurations, the 99.5ms (MAX) is required, and the Hub and its associated circuitry must not consume more than 100mA from the upstream USB power source during t2+t3+t4+t5+t6+t7. For Self-Powered configurations, t3 MAX is not applicable and the time to load the configuration is determined by the external SMBus host. All Power Supplies must have reached the operating levels mandated in Section Chapter 7, "DC Parameters", prior to (or coincident with) the assertion of RESET_N.
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5.6.2
USB Bus Reset
In response to the upstream port signaling a reset to the Hub, the Hub does the following:
Note: The Hub does not propagate the upstream USB reset to downstream devices.
1. Sets default address to 0. 2. Sets configuration to: Unconfigured. 3. Negates PRTPWR to all downstream ports. 4. Clears all TT buffers. 5. Moves device from suspended to active (if suspended). 6. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence. The Host then configures the Hub and the Hub's downstream port devices in accordance with the USB Specification.
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Chapter 6 XNOR Test
XNOR continuity tests all signal pins on the Hub (every pin except for NC, XTAL1/CLKIN, XTAL2, ATEST/REG_EN, RBIAS, TEST, Power, and Ground). This functionality is enabled by driving TEST and CFG_SEL[1] high, driving SCLK low and transition RESET_N from low to high. The output from the XNOR chain is driven to GR2 . For each pin tested for continuity GR2 should toggle.
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Chapter 7 DC Parameters
7.1 Maximum Guaranteed Ratings
SYMBOL MIN MAX UNITS COMMENTS
PARAMETER
Storage Temperature Lead Temperature 1.8V supply voltage 3.3V supply voltage
TA
-55
150 325
C C V Soldering < 10 seconds
VDDA18PLL VDD18 VDDA33 VDDA33PLL VDD33CR
-0.3
2.5
-0.3
4.0
V
Voltage on any I/O pin Voltage on XTAL1 Voltage on XTAL2
-0.3 -0.3 -0.3
(3.3V supply voltage + 2) 6 4.0 VDD18 + 0.3V
V V V
Note: Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
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7.2
Recommended Operating Conditions
PARAMETER SYMBOL MIN MAX UNITS COMMENTS
Operating Temperature 1.8V supply voltage 3.3V supply voltage
TA VDDA18PLL VDD18 VDDA33 VDDA33PLL VDD33CR
0 1.62 3.0
70 1.98 3.6
C V V
Voltage on any I/O pin
-0.3
5.5
V
If any 3.3V supply voltage drops b e l o w 3 . 0 V, t h e n t h e M A X becomes: (3.3V supply voltage + 0.5)
Voltage on XTAL1 Voltage on XTAL2
-0.3 -0.3
VDDA33 VDD18
V V
Table 7.1 DC Electrical Characteristics PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I, IS Type Input Buffer Low Input Level High Input Level Input Leakage Hysteresis (`IS' Only) Input Buffer with Pull-Up (IPU) Low Input Level High Input Level Low Input Leakage High Input Leakage Input Buffer with Pull-Down IPD Low Input Level High Input Level Low Input Leakage High Input Leakage
SMSC USB2502
VILI VIHI IIL VHYSI 2.0 -10 250 300
0.8
V V
TTL Levels
+10 350
uA mV
VIN = 0 to VDD33CR
VILI VIHI IILL IIHL 2.0 +5 -10
0.8
V V
TTL Levels
+45 +10
uA uA
VIN = 0 VIN = VDD33CR
VILI VIHI IILL IIHL 2.0 +10 -80
0.8
V V
TTL Levels
-10 -160
uA uA
VIN = 0 VIN = VDD33CR
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Table 7.1 DC Electrical Characteristics (continued) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
ICLK Input Buffer Low Input Level High Input Level Input Leakage Hysteresis O8 and I/O8 Type Buffer Low Output Level High Output Level Output Leakage VOL VOH IOL 2.4 -10 +10 0.4 V V uA VILCK VIHCK IIL VHYSC 2.0 -10 50 +10 100 0.8 V V uA mV VIN = 0 to VDD33CR TTL Levels
IOL = 8 mA @ VDD33CR = 3.3V IOH = -4mA @ VDD33CR = 3.3V VIN = 0 to VDD33CR (Note 1)
I/OSD12 Type Buffer Low Output Level Output Leakage Hysteresis IO-U (Note 2) I-R (Note 3) Supply Current Unconfigured High-Speed Host Full-Speed Host Supply Current Configured (High-Speed Host) 2 Ports @ FS/LS 2 Ports @ HS 1 Port HS, 1 Port FS/LS Supply Current Configured (Full-Speed Host) 1 Port 2 Ports IFCC1 IFCC2 90 90 mA mA IHCC2 IHCH2 120 170 140 mA mA mA ICCINIT ICCINIT 73 65 mA mA Total from all supplies VOL IOL VHYSI -10 250 300 0.4 +10 350 V A mV IOL = 12 mA @ VDD33CR = 3.3V VIN = 0 to VDD33CR (Note 1)
IHCH1C1
Total from all supplies
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Table 7.1 DC Electrical Characteristics (continued) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
Supply Current Suspend Supply Current Reset
Notes:
ICSBY IRST
320 160
425 300
uA uA
Total from all supplies. Total from all supplies.
1. Output leakage is measured with the current pins in high impedance. 2. See USB 2.0 Specification for USB DC electrical characteristics. 3. RBIAS is a 3.3V tolerant analog pin.
CAPACITANCE TA = 25C; fc = 1MHz; VDD33CR = 3.3V LIMITS PARAMETER SYMBOL MIN TYP MAX UNIT TEST CONDITION
Clock Input Capacitance Input Capacitance Output Capacitance
CIN CIN COUT
12 8 12
pF pF pF
All pins except USB pins (and pins under test tied to AC ground)
Power Sequencing
There are no power supply sequence restrictions for the Hub. The order in which power supplies power-up and power-down is implementation dependent.
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Chapter 8 AC Specifications
8.1 Oscillator/Clock
Crystal: Parallel Resonant, Fundamental Mode, 24 MHz 100ppm. External Clock: 50% Duty cycle 10%, 24 MHz 100ppm, Jitter < 100ps rms.
8.1.1
SMBus Interface:
The SMSC Hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the SMBus 1.0 Specification for Slave-Only devices (except as noted in Section 5.3).
8.1.2
I2C EEPROM:
Frequency is fixed at 59KHz 20%.
8.1.3
USB 2.0
The Hub conforms to all voltage, power, and timing characteristics and specifications as set forth in the USB 2.0 Specification. Please refer to the USB Specification for more information.
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Chapter 9 Package Outlines
REVISION HISTORY
REVISION DESCRIPTION SEE SPEC FRONT PAGE FOR REVISION HISTORY DATE RELEASED BY -
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Datasheet
2-Port USB 2.0 Hub Controller
D 3 TERMINAL #1 IDENTIFIER AREA (D1/2 X E1/2) D1 e
D2
-
TERMINAL #1 IDENTIFIER AREA (D/2 X E/2)
3
E1
E
E2
EXPOSED PAD
4
0.6(MAX)
36X L
0.6(MAX)
36X 0.2 MIN
36X b 2
CHAMFERED CORNERS ARE OPTIONAL 4X
TOP VIEW
BOTTOM VIEW
4X 0-12 C 4 ccc C A1 A3 A2 A
SIDE VIEW
D2 / E2 VARIATIONS CATALOG PART
3-D VIEWS
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN MILLIMETERS AND TOLERANCES ARE: DECIMAL 0.1 X.X X.XX 0.05 X.XXX 0.025 ANGULAR 1
THIRD ANGLE PROJECTION
80 ARKAY DRIVE HAUPPAUGE, NY 11788 USA
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETER. 2. POSITION TOLERANCE OF EACH TERMINAL IS 0.05mm AT MAXIMUM MATERIAL CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED. 4. COPLANARITY ZONE APPLIES TO EXPOSED PAD AND TERMINALS.
TITLE
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
NAME
DRAWN
DATE
-
S.K.ILIEV
CHECKED
12/6/04 12/6/04
PACKAGE OUTLINE 36 TERMINAL QFN, 6x6mm BODY, 0.5mm PITCH
DWG NUMBER
FINISH
S.K.ILIEV
APPROVED
MO-36-QFN-6x6
STD COMPLIANCE SHEET
REV
F 1 OF 1
PRINT WITH "SCALE TO FIT" DO NOT SCALE DRAWING
SCALE
S.K.ILIEV
12/6/04
1:1
JEDEC: MO-220
Figure 9.1 36 Pin QFN Package
2-Port USB 2.0 Hub Controller Datasheet
Figure 9.2 48 Pin TQFP Package Outline (7x7x1.4 mm body, 2mm Footprint) Table 9.1 48 Pin TQFP Package MIN NOMINAL MAX REMARKS
A A1 A2 D D1 E E1 H L L1
~ 0.05 1.35 8.80 6.90 8.80 6.90 0.09 0.45 ~ 0o 0.17 0.08 0.08 ~
Notes:
e
W R1 R2 ccc
~ ~ ~ ~ ~ ~ ~ ~ 0.60 1.00 0.50 Basic ~ 0.22 ~ ~ ~
1.60 0.15 1.45 9.20 7.10 9.20 7.10 0.20 0.75 ~ 7o 0.27 ~ 0.20 0.08
Overall Package Height Standoff Body Thickness X Span X body Size Y Span Y body Size Lead Frame Thickness Lead Foot Length Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
1. Controlling Unit: millimeter. 2. Tolerance on the true position of the leads is 0.04 mm maximum. 3. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm. 4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane. 5. Details of pin 1 identifier are optional but must be located within the zone indicated.
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